1. Field of the Invention
The invention relates generally to information processing systems. More particularly, this invention relates to control and data signal transfers within a computer system having a multiple bus architecture.
2. Description of the Related Art
Information processing systems, such as personal computers (PCs), have virtually become an inseparable part of everyone""s daily activities. These systems process an enormous amount of information in a relatively short time. To perform these sophisticated tasks, a computer system typically includes a microprocessor, memory modules, various system and bus control units, and a wide variety of data input/output (I/O) and storage devices. These computer components communicate control and data signals using various data rates and signal protocols over multiple system buses. The demand for faster processing speed, and the revolutionary fast-rack development of computer systems, have necessitated the use of interconnecting devices. These devices act as compatibility bridges among various data transfer protocols within the computer system. One example of such interconnecting devices is the peripheral component interconnect (PCI) bridge.
The PCI Local Bus Specification, Revision 2.1 (xe2x80x9cPCI Specificationxe2x80x9d) defines a PCI Local Bus with the primary goal of establishing an industry standard. The PCI Local Bus is a 32-bit or 64-bit bus with multiplexed address and data lines. The bus is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The PCI Specification includes the protocol, electrical, mechanical, and configuration specification for PCI Local Bus components and expansion boards.
FIG. 1 shows an exemplary computer system using a conventional bus architecture. As shown in FIG. 1, a central processor unit (CPU) 100 is connected to a Host bus 110. On the Host bus 110, a plurality of host bus compatible devices (not shown in this figure) may be connected to access and exchange control and data signals with the CPU 100. Typically, a Host-PCI bridge 120 is employed to connect the Host bus 110 to a PCI Bus 0130. The Host-PCI bridge 120 allows one or more PCI device to access devices that are resident on the Host bus 110 (e.g., the CPU 100). Typical PCI devices (xe2x80x9cpeer devicesxe2x80x9d) include an audio card, a motion video card, a local area network (LAN) interface, a small computer system interface (SCSI), an expansion bus interface, a graphics card, or other PCI-PCI bridges.
To support industry standard architecture (ISA) devices, a PCI-ISA bridge 140 is used to connect an ISA bus 150 to the PCI bus 0130. ISA devices may include a floppy drive, a key board, a mouse, a serial port, a parallel port, a read only memory (ROM) unit, a real-time clock (RTC), and/or an audio interface (not shown in this figure). In addition to the PCI-ISA bridge 140, one or more PCI-PCI bridges may be connected to the PCI bus 0130 to generate additional PCI buses. Two PCI-PCI bridges are implemented including a PCI-PCI bridge 160 which generates a PCI bus 1170, and a PCI-PCI bridge 180 which generates a PCI bus 2190. The additional PCI buses 170 and 190 support additional PCI devices.
The PCI Specification provides for software driven initialization and configuration via a Configuration Address Space. Typically, systems provide a mechanism that allows generation of PCI configuration cycles by software. This mechanism is typically located in the Host-PCI bridge 120. PCI devices are often required to provide 256 bytes of configuration registers for this purpose. Each PCI device decodes its own address for normal accesses. To support hierarchical PCI buses, two types of configuration access are typically used: Type 0 and Type 1. Type 0 configuration accesses do not propagate beyond the local PCI bus (i.e., PCI bus 0130). Hence, Type 0 configuration accesses are claimed by a local PCI device (i.e., resident on PCI bus 0130). Whereas, a Type 1 configuration access is used when the target PC device of a configuration access resides on another PCI bus (i.e., not the local PCI bus). Type 1 accesses are ignored by all target devices except PCI-PCI bridges. A PCI-PCI bridge (e.g., PCI-PCI bridge 160) decodes a Bus Number field from the configuration access to determine if the destination of the configuration access is resident behind the PCI-PCI bridge. Accordingly, the PCI-PCI bridge 160 claims the configuration access if the access is to a bus behind the PCI-PCI bridge 160 (the xe2x80x9csecondary busxe2x80x9d). If the Bus Number is not for a bus behind the PCI-PCI bridge 160, the PCI-PCI bridge 160 ignores the configuration access. If the Bus Number matches the secondary bus (i.e., PCI bus 2190) of the PCI-PCI bridge 160, the PCI-PCI bridge 160 converts the Type 1 configuration access into a Type 0 configuration access. Then, a Device Number is decoded from the configuration access to select one of 32 devices on the local bus. The PCI-PCI bridge 160 asserts the correct Device Select and initiates a configuration access.
Recently, an OnNow design initiative was introduced as a comprehensive, system-wide approach to system and device power control. OnNow is a term for a PC that is always on but appears off and responds immediately to user or other requests. The OnNow design initiative involves changes that will occur in both the Microsoft Windows 98 and Windows NT operating systems, device drivers, hardware, and applications. OnNow relies on the changes defined in the Advanced Configuration and Power Interface (ACPI) v. 1.0 specification. The ACPI specification defines standards which enable PC systems to automatically turn on and off peripherals such as CD-ROMs, network cards, hard disk drives, and printers.
A configuration cycle comprises a series of read and/or write actions executed to set a device in a desired state or mode of operation. On a host bus, the configuration cycle is sometimes referred to as the xe2x80x9cconfiguration transaction.xe2x80x9d On a PCI bus, the configuration cycle is commonly referred to as the xe2x80x9cconfiguration cycle.xe2x80x9d For the purpose of this disclosure, the term xe2x80x9cconfiguration cyclexe2x80x9d is used to mean either xe2x80x9cconfiguration cyclexe2x80x9d or xe2x80x9cconfiguration transaction.xe2x80x9d In an attempt to speed up configuration cycles, and satisfy design initiatives such as OnNow, a watchdog timer may be implemented in the Host-PCI bridge 120. Upon initiating a configuration cycle by the CPU 100, and if a peer device is present in the system, the peer device responds to the configuration cycle. If a peer device is not installed in the system, the watchdog timer terminates the cycle after a predetermined critical time. If this critical time is too short, then configuration cycles for present peer devices may be terminated prematurely, thereby causing a system failure. If, on the other hand, the critical time is too long, then the system takes excessive time to configure peer devices and boot up the system. Laboratory measurements have shown that, while a system boot up is more certain with a longer critical time, the system may take several seconds longer than necessary to boot up. This excessive boot up time is incompatible with the new fast boot up standards, such as OnNow. Therefore, there is a need in the technology to expedite the configuration cycles without causing a system failure.
To overcome the above-mentioned problems, the invention provides a system for autonomously configuring peer devices without the unnecessary delay in boot up time. The system determines whether a configuration cycle is intended for a peer device on the Host bus, or for a device which may exist on the Local PCI bus. Once the presence of each peer device is determined, no further bus time-outs need occur.
In accordance with one embodiment of the invention, a system for configuring devices in an information processing system having first and second buses is provided. The system comprises a processor which initiates a configuration cycle to a device over the first bus. The system further comprises a bridge connected to the processor via the first bus. The bridge monitors the configuration cycle on the first bus, and communicates the configuration cycle to the second bus if the device does not respond to the configuration cycle. In another embodiment of the invention, the system comprises a processor which initiates a configuration cycle to a device over the first bus. The system further comprises a bridge connected to the processor via the first bus. The bridge communicates the configuration cycle to the second bus, and determines whether to utilize the result of the configuration cycle on the second bus.